1. Field of the Invention
This invention, generally, relates to Complementary Metal Oxide Semiconductor (CMOS) integrated circuits. More specifically, the invention relates to Multi-Threshold CMOS circuits capable of operating in active and standby modes.
2. Background Art
Modem Integrated Circuits (IC's) are designed to provide an enormous amount of functionality in a small area. Very large scale IC's are able to provide nearly all the functions required in many high-performance microprocessor designs and electronic devices. However, a significant portion of the total power consumption in high-performance digital circuits is due to leakage currents (both sub-threshold and gate). Besides, the ability to incorporate vast processing power and multiple functions has made IC's nearly indispensable in portable electronic devices. Portable electronic devices, such as a notebook computers, personal digital assistants, and cellular phones require IC's that have the ability to perform highly complex tasks. Portable electronic device designers, in turn, are committed to increasing the functionality of the device while reducing its physical size.
One method of increasing the functionality of a portable electronic device is to increase the number of functions performed by the IC's. However, in order to keep the size of the IC from becoming prohibitively large, IC designers have been decreasing the physical size of the transistors used in the circuit design. The dimensions of the transistors used in a typical IC are limited by the techniques used to create them. Presently, IC transistors have dimensions on the order of sub-microns. For example, in sub-micron IC technology, the length (L) of a Metal Oxide Semiconductor (MOS) transistor may be less than 1 μm.
The physical size of portable electronic devices cannot be decreased merely by incorporating more functionality into the IC's. Increases in the complexity and functionality of the IC scales the power consumption of the IC proportionally. Because most portable electronic devices are battery powered, power consumption plays an important part in determining the useful operational time of a portable device. Increasing the capacity of the battery may increase the operational time of a portable device, however, this option is in conflict with the desire to decrease the physical size and weight of portable devices. Thus, there is a corresponding need to reduce the power consumed in the portable electronic device. Decreasing the power consumption allows the designer to incorporate a battery having smaller capacity, and typically smaller physical size.
The IC designer is thus tasked with increasing the complexity of the IC while simultaneously decreasing the power consumption. One manner of decreasing the power consumed by the IC is by judicious selection of the type of technology used in implementing the IC. An IC may be implemented using a variety of technologies. For example, circuits may be implemented using bipolar transistors, Metal Oxide Semiconductor (MOS) transistors, NMOS transistors, and Complementary MOS (CMOS) transistors. CMOS transistor implementations are particularly favored in digital designs because a CMOS gate, theoretically, consumes no power in a static state.
Power is consumed by a CMOS circuit when the circuit switches between logic states. A significant reduction in CMOS power consumption can be achieved by reducing the power supply voltage to the circuits. Doing this, however, adversely affects the propagation delays of CMOS circuits, degrading the ability of the CMOS gate to function in a high speed circuit.
Power consumption of CMOS circuits can also be reduced without greatly degrading the high speed characteristics of the circuit by implementing both high threshold voltage transistors along with low threshold voltage transistors onto the same IC design. These circuits are referred to as Multi-Threshold CMOS (MTCMOS) circuits.
Previous MTCMOS implementations have connected the low threshold voltage circuits to virtual power supply lines and virtual voltage common lines. The virtual power supply and voltage common lines are electrically connected to the actual power supply or voltage common lines using high threshold power transistors. During active modes, the high threshold voltage power transistors are conducting and connect the low threshold voltage transistors to the actual power supply line and the actual voltage common line. During stand by modes, the high threshold voltage power transistors are turned off. The virtual power supply lines are effectively shut off, thus shutting down all of the low threshold voltage transistors connected to the virtual power supply lines.
Multi-threshold CMOS (MTCMOS) is a very efficient technique for controlling standby leakage. It uses a high threshold MOS device to de-couple the logic from the supply or ground during long idle periods, or standby states. The main concern in the implementation of MTCMOS scheme is the trade-off among standby leakage power, increased area, process/mask complexity, and active mode performance.
Active body biasing has been proposed to enhance MTCMOS scheme for bulk CMOS and partially depleted SOI (PD-SOI) circuits. For bulk CMOS, the triple well technology is required. For SOI, this scheme is only suited to thick silicon film SOI. Forming adequate body ties is becoming challenging and requires additional masking layers and implants to avoid creating a fully depleted region in the body tie structure, which would result in an open circuit to the body. The silicon thickness in scaled SOI devices has been aggressively scaled to reduce the junction capacitance and for better short channel control. For the silicon film down to 7-15 nm, it becomes almost impossible to offer body-contact in SOI. Furthermore, the area penalty to have a body contact to an SOI device is quite significant.
Recently a hybrid CMOS structure for body ties in ultra-thin SOI has been proposed. That proposal offers a hybrid CMOS structure that has both UTSOI CMOS and bulk CMOS FETs. The bulk CMOS FETs would be used in circuit application where well-bias scheme is applied and Vt tolerance is important. Furthermore, several technology approaches such as double SIMOX bonded HOT substrate, have been proposed to implement both (100) SOI nFETs and (110) SOI pFETs on one wafer, which is called “super HOT”.
Also proposed recently is a high-performance high-VT, thick-oxide pFET header in hybrid orientation technology, where the higher mobility of (110) pFET is utilized to enhance the performance of the pFET header. In that scheme, one of the devices (say NFET) is placed in SOI, while the other (i.e. pFET) is placed in the epitaxial layer, or vice versa. So, the logic transistors consist of mixed SOI-epitaxial devices. As such, the “bulk” device on the epitaxial layer suffers from added junction capacitances and reverse-body effect in stacked or pass-transistor configurations, thus degrading the performance of the logic circuits. Furthermore, the pFET header device is in the same substrate as all the logic pFETs. If the pFETs are in the epitaxial layer, it would be impractical to apply body/well bias to the header pFETs since it is difficult to isolate the well for the header pFETs. If the pFETs are in SOI, individual body bias can be applied to the header pFETs. However, the area penalty associated with individual body contacts can be significant. Moreover, for ultra-thin SOI (UTSOI), it would be impossible to offer good/effective body contacts.